69: Microstructure-Performance Evolution in Lanthanum-Doped Ferroelectric HZO MIM Capacitors by Precession Electron Diffraction

International Conference on Solid State Devices and Materials, Nagasaki, Japan Sept 14 - 17, 2026

Sarah Lynch, Hannah Margavio, Sara Aoki, Dina Triyoso, Steve Consiglio, Dave Hetzer, Cory Wajda, Gert Leusink, Rinus Lee

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68: Area-Selective Molecular Layer Deposition of Polyamide on EUV Resists versus Si-Based Underlayers for 300mm Wafer Processing

Area Selective Deposition Workshop, Albany NY, USA Mar 29 - Apr 1, 2026

Van Long Nguyen, Christophe Vallee, Ornella Sathoud, Jonathan Abreu, Rinus Lee, Danny Newman, Cory Wajda, Kandabara Tapily, Gert Leusink

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67: (Invited) Innovations in Process Technology Enabling Next Generation Memory Solutions

IEEE Electron Device Technology and Manufacturing, Penang, Malaysia Mar 1 - 4, 2026

Rinus Lee, S. Lynch, J. Grasso, S. Aoki, T.Basu, D. O'Meara, J. Maguire, Y. Qin, E. Sweet, R. Soedibyo, K. Tapily, D. Triyoso, H. Aizawa, C. Wajda

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66: Impact of Metal Underlayers on EUV Lithography Performance with Sn-Based Metal Oxide Resists

SPIE Advanced Lithography + Patterning Conference, San Jose CA, USA Feb 22 - 26, 2026

T. Miyahara, D. Hamashita, K. Imakita, J. Huang, J. Oakley, N. Okabe, K. Yamada, H. Aizawa, R. Lee

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65: Ab-Initio Investigation of Fundamental Reaction Mechanisms, Environmental Effects and EUV Reactivity of Sn-Based Metal Oxide Photoresists

SPIE Advanced Lithography + Patterning Conference, San Jose CA, USA Feb 22 - 26, 2026

N. Liza, ​K. Yamada, A. Agawarl, I. Simms, R. Burns, T. Omatsu, R. Lee, M. Muramatsu, H. Cheng, R. Yamaguchi

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64: The Systematic Study of NbOx Inter Layer for Ferroelectric Memory

IEEE Semiconductor Interface Specialist Conference, San Diego CA, USA Dec 10 -13, 2025

S. Aoki, R. Soedibyo, S. Lynch, K. Imakita, Y. Otsuki, D. O’Meara, D. Triyoso, K. Tapily, R. Lee, H. Aizawa

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63: (Invited) Transfer Learning on Edge Using 14nm CMOS-compatible ReRAM Array and Analog In-memory Training Algorithm

International Electron Device Meeting (IEDM), San Francisco CA, USA, Dec 6 - 10, 2025

Takashi Ando, Omobayode Fagbohungbe, Kenichi Imakita, Hiroyuki Miyazoe, Sara Aoki, Ruturaj Pujari, Sarah Lynch, Paul Jamison, Kevin Brew, Kishore Natarajan, Gerald Gibson, Robert Bruce, Rinus Lee, Cory Wajda, Takaaki Tsunomura, Vijay Narayanan

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62: (Invited) Interconnect Technology for the Angstrom Era and Beyond

International Workshop on Junction Technology, Kyoto, Japan, June 4 - 6, 2025

Rinus T.P. Lee, K. Imakita, G. Pattanaik, R. Yonezawa, K.H. Yu, J. Mayersky, H. Suzuki, C. Wajda

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61: Development of High Thermal Conductance Wafer Bonding Interface With PVD Aluminum Nitride

IEEE 75th Electronic Components and Technology Conference (ECTC), Dallas, Texas, USA, May 27 - 30, 2025

Andrew Tuchman, Ayuta Suzuki, Christopher Netzband, Joshua Greklek, Rinus Lee, Ilseok Son

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60: Process Control for the Modification of Ruthenium Resistivity in Scaled Subtractive Interconnects

IEEE International Conference on Interconnect Technology, San Jose, California USA, June 3 – 6, 2024

Jack Rogers, Hirokazu Aizawa, Nicholas Joy, Rinus Lee, Kenichi Imakita, Hojin Kim, Toru Hisamatsu

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59: Thickness-Dependent Optical Properties of Metallic Thin Films and Their Correlation with Thermal Conductivity
Materials Research Society (MRS) Spring Meeting, Seattle, Washington, USA, April 23, 2024
Saman Zare, Md. Rafiqul Islam, Sean King, Christopher Jezewski, Colin Landon, Rinus Lee, Kanda Tapily, Colin Carver, Patrick Hopkins

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58: A Study of Resistivity Control for Subtractive Interconnects Using Ruthenium
IEEE International Conference on Interconnect Technology, Dresden, Germany, May 22 – 25, 2023
Jack Rogers, Hirokazu Aizawa, Nicholas Joy, Sophia Rogalskyj, Rinus Lee, Kenichi Imakita, Kai-Hung Yu

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57: Measuring the Phonon Contributions to Total Thermal Conductivity of Ruthenium and Tungsten Thin Films using a Steady-State Thermoreflectance Technique
American Physical Society March Meeting, Las Vegas, Nevada, USA, March 5 – 10, 2023
Md Rafiqul Islam, S. W King, K. Tapily, D. H Hirt, J. Tomko, C. Jezewski, C.D. Landon, K. Aryana, C. Carver, P. Hopkins, E.R. Hoglund, Rinus T.P. Lee

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56: (Invited) Materials and Process Technologies for Scaling BEOL Interconnects
239th Electrochemical Society Meeting, (Virtual), May 30 – June 3, 2021
Rinus T.P. Lee, K. H. Yu, G. Pattanaik, R. Bourque, C. S. Wajda, and G. J. Leusink

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55: Yield and Failure Analysis of FinFET Source to Drain Leakage in 14nm Technology
International Symposium for Testing and Failure Analysis, November 2020 (Virtual)
F. Beaudoin, S. Kodali, R. Deshpande, W. Zhao, E. Banghart, Rinus Lee, T. Mahalingam, Nuh Yusek, Wang Tao, Lillian Li, Sushruth Goud Perumalla, Shweta Arora, Trejo Rust

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54: Nanosecond Laser Anneal for BEOL Performance Boost in Advanced FinFETs
Symposium on VLSI Technology, Honolulu, HI, USA, June 2018
Rinus T.P. Lee, N. Petrov, J. Kassim, M. Gribelyuk, J. Yang, L. Cao, K.B. Yeap, T. Shen, A.N. Zainuddin, A. Chandrashekar, S. Ray, E. Ramanathan, A.S. Mahalingam,

R. Chaudhuri, J. Mody, D. Damjanovic, Z. Sun, R. Sporer, T.J. Tang, H. Liu, J. Liu, B. Krishnan

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53: (Invited) Low Temperature Microwave Annealing for CMOS Scaling 
China Semiconductor Technology International Conference (CSTIC), Shanghai, China, March 2018
Rinus T.P. Lee, J. Kassim, R. Krishnan, B. Kannan, J. Rowland, A. Madan, D. Ferrer, J. Yang, S. Byrappa, J. Mody, M. Gribelyuk, W. Zhao, E. Kaganer, B. Yatzor, L. Huang,

J.P. Liu, B. Krishnan

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52: (Late News) A 7nm CMOS Technology Platform for Mobile and High Performance Compute Application 
International Electron Device Meeting (IEDM), San Francisco CA, USA, Dec 2017
S. Narasimha, B. Jagannathan, A. Ogino, D. Jaeger, B. Greene, C. Sheraw, K. Zhao, B. Haran, U. Kwon, A.K.M. Mahalingam, B. Kannan, B. Morganfeld, J. Dechene, C. Radens, A. Tessier, A. Hassan, H. Narisetty, I. Ahsan, M. Aminpur, C. An, M. Aquilino, A. Arya, R. Augur, N. Baliga, R. Bhelkar, G. Biery, A. Blauberg, N. Borjemscaia, A. Bryant, L. Cao, V. Chauhan, M. Chen, L. Cheng, J. Choo, C. Christiansen, T. Chu, B. Cohen, R. Coleman, D. Conklin, S. Crown, A. da Silva, D. Dechene, G. Derderian, S. Deshpande, G. Dilliway, K. Donegan, M. Eller, Y. Fan, Q. Fang, A. Gassaria, R. Gauthier, S. Ghosh, G. Gifford, T. Gordon, M. Gribelyuk, G. Han, J.H. Han, K. Han, M. Hasan, J. Higman, J. Holt, L. Hu, L. Huang, C. Huang, T. Hung, Y. Jin, J. Johnson, S. Johnson, V. Joshi, M. Joshi, P. Justison, S. Kalaga, T. Kim, W. Kim, R. Krishnan, B. Krishnan, Anil K., M. Kumar, J. Lee, R. Lee, J. Lemon, S.L. Liew, P. Lindo, M. Lingalugari, M. Lipinski, P. Liu, J. Liu, S. Lucarini, W. Ma, E. Maciejewski, S. Madisetti, A. Malinowski, J. Mehta, C. Meng, S. Mitra, C. Montgomery, H. Nayfeh, T. Nigam, G. Northrop, K. Onishi, C. Ordonio, M. Ozbek, R. Pal, S. Parihar, O. Patterson, E. Ramanathan, I. Ramirez, R. Ranjan, J. Sarad, V. Sardesai, S. Saudari, C. Schiller, B. Senapati, C. Serrau, N. Shah, T. Shen, H. Sheng, J. Shepard, Y. Shi, M.C. Silvestre, D. Singh, Z. Song, J. Sporre, P. Srinivasan, Z. Sun, A. Sutton, R. Sweeney, K. Tabakman, M. Tan, X. Wang, E. Woodard, G. Xu, D. Xu, T. Xuan, Y. Yan, J. Yang, K.B. Yeap, M. Yu, A. Zainuddin, J. Zeng, K. Zhang, M. Zhao, Y. Zhong, R. Carter,C-H. Lin, S. Grunow, C. Child, M. Lagus, R. Fox, E. Kaste, G. Gomba, S. Samavedam, P. Agnello, and DK Sohn

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51: (Invited) Benchmarking Source/Drain Doping and Contact Technology Options for III-V Semiconductor Devices
9th International Conference on Materials for Advanced Technologies, Singapore, June 2017
Rinus T.P. Lee

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50: Effects of Metal Orientation and Alloying on Metal-Semiconductor Schottky Barriers 
APS March Meeting, New Orleans, LA, March 2017
Eduardo C. Silva, Domingo A. Ferrer, Israel Ramirez , Praneet Adusumilli , Oscar D. Restrepo, Rinus Lee, Wonwoo Kim, Murali Kota

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49: (Invited) Heterogeneous Integration of III-V Semiconductors on Silicon for Electronics
229th ECS Meeting, San Diego CA, USA, June 2016
Rinus T.P. Lee

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48: 10nm Nominal Channel Length MoS2 FETs with EOT 2.5nm and 0.52mA/um Drain Current 
Device Research Conference, Columbus OH, USA, June 2015
L. Yang, R.T.P. Lee, S.S. Papa Rao, W. Tsai and P.D. Ye

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47: (Invited) Technology Options to Reduce Contact Resistance in Nanoscale III-V MOSFETs
227th ECS Meeting, Chicago IL, USA, May 24 – 28, 2015
Rinus T.P. Lee, W.Y. Loh, R. Tieckelmann, T. Orzali, C. Huffman, A. Vert, G. Huang, M. Kelman, Z. Karim, C. Hobbs, R.J.W Hill and S.S. Papa Rao

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46: Arsenic Monolayer Doping for Si and Ge Semiconductors
Surface Preparation and Cleaning Conference (SPCC) Saratoga Springs, NY, USA, May 12 – 14, 2015
W.-Y. Loh, C.H. Chen, R. Tieckelmann, Rinus T.P. Lee, E. Bersch, B. Sapp, C. Hobbs, S. Papa Rao, T. Cameron, T. Baum, J.-F. Zheng, S. Dimascio, D. Elzer, A. Avila, J. O’Neil, K. Fuse, M. Sato, N. Fujiwara, L. Chang, H. Uchida 

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45: 300mm Wafer Level Sulfur Monolayer Doping for III-V Materials 
Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs NY, USA, May 3 – 6, 2015 
W.Y. Loh, R.T.P. Lee, R. Tieckelmann, T. Orzali, B. Sapp, C. Hobbs, S.S. Papa Rao, K. Fuse, M. Sato, N. Fujiwara, L. Chang and H. Uchida

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44: Ultra Low Contact Resistivity (<1×10-8 Ω-cm2) to In0.53Ga0.47As Fin Sidewalls (110)/(100) Surfaces: Realized with a VLSI Processed III-V Fin TLM Structure fabricated with III-V on Si Substrates
International Electron Device Meeting (IEDM), San Francisco CA, USA, Dec 15 – 17, 2014
Rinus T.P. Lee, Y. Ohsawa, C. Huffman, Y. Trickett, G. Nakamura, C. Hatem, K.V. Rao, F. Khaja, R. Lin, K. Matthews, A Jensen, T. Karpowicz, Peter F. Nielsen, E. Stinzianni,

A. Cordes, P.Y. Hung, D.-H. Kim, R.J.W. Hill, W.Y. Loh, C. Hobbs

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43: VLSI processed InGaAs on Si MOSFETs with Thermally Stable, Self-Aligned Ni-InGaAs Contacts Achieving: Enhanced Drive Current and Pathway Towards a Unified Contact Module
International Electron Device Meeting (IEDM), Washington, DC, USA, December 9 – 11, 2013
Rinus T.P. Lee, R.J.W Hill, W-Y Loh, R-H Baek, S. Deora, K. Matthews, C. Huffman, K. Majumdar, T. Michalak, C. Borst, P.Y. Hung, C-H Chen, J-H Yum, T-W Kim, C.Y. Kang, W-E Wang, D-H Kim, C. Hobbs, P.D. Kirsch

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42: High Voltage GaN Technology in a Silicon CMOS Environment: Challenges and Opportunities 
224th ECS Meeting, San Francisco, CA, Oct 27 – Nov 1, 2013
Rusty Harris, Derek W Johnson, Richard J.W. Hill, Ed Piner, Man Hoi Wong, Rinus T.P. Lee

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41: Relays do not leak – CMOS does
50th Design Automation Conference (DAC), Austin, TX, USA, May 29 – June 7, 2013
H. Fariborzi, Fred Chen, R. Nathanael, I-R. Chen, L. Hutin, R. Lee, T.-J. K. Liu

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40: ETB-QW InAs MOSFET with Scaled Body for Improved Electrostatics 

International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 10 – 13, 2012
T-W Kim, D-H Kim, D-H Koh, RJW Hill, Rinus T.P. Lee, Man Hoi Wong, T. Cunningham, Jesús A Del Alamo, Sanjay Kumar Banerjee, S. Oktyabrsky, A. Greene, Y. Ohsawa, Y. Trickett, G. Nakamura, Qiang Li, Kei May Lau, C. Hobbs, Paul D Kirsch, Raj Jammy

 

39: (Invited) Emerging CMOS and Beyond CMOS Technologies for an Ultra-Low Power 3D World 
IEEE International Conference on IC Design & Technology (ICICDT), Austin, TX, USA, May 30 – Jun 1, 2012
C.Y. Kang, K.W. Ang, R. Hill, W.Y. Loh, J Oh, R. Lee, David Gilmer, Gennadi Bersuker, C. Hobbs, Paul Kirsch, Klaus Hummler, S. Arkalgud, Raj Jammy​

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38: (Invited) Integration Challenges of III-V Materials in Advanced CMOS Logic
221st ECS Meeting. Seattle, Washington, May 6-10, 2012
R. J. W. Hill, W.Y. Loh, J. Huang, T. Kim, R. Lee, W.E. Wang, J. Oh, C. Hobbs, P. D. Kirsch, R. Jammy

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37: Scaled Micro-Relay Structure with Low Strain Gradient for Reduced Operating Voltage
221st ECS Meeting. Seattle, Washington, May 6-10, 2012
I-Ru Chen, Louis Hutin, Chanro Park, Rinus Lee, Rhesa Nathanael, Jack Yaung, Jaeseok Jeon, Tsu-Jae King Liu

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36: (Invited) Challenges of III–V materials in Advanced CMOS logic
VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr 23 – 25, 2012
P.D. Kirsch, R.J.W Hill, J Huang, W.Y. Loh, T-W Kim, M.H. Wong, B.G. Min, C. Huffman, D. Veksler, C.D. Young, K.W. Ang, I. Ali, R.T.P. Lee, T. Ngai, A. Wang, W-E Wang,

T.H. Cunningham, Y.T. Chen, P.Y. Hung, E. Bersch, B. Sassman, M. Cruz, S. Trammell, R. Droopad, S. Oktybrysky, J.C. Lee, G. Bersuker, C. Hobbs, R. Jammy

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35: Silicon-Carbon S/D Stressors: Integration of a Novel Nickel Aluminide-Silicide and Post-SPE Anneal for Reduced Schottky-Barrier and Leakage
216th ECS Meeting, Vienna, Austria, October 4 – 9, 2009
S.M. Koh, Wei-Jing Zhou, Rinus T.P. Lee, Mantavya Sinha, Chee-Mang Ng, Zhiyong Zhao, Helen Maynard, Naushad Variam, Yuri Erokhin, Ganesh Samudra, Yee-Chia Yeo

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34: (Invited) Advanced Contact Technology for MOSFETs: Integration of New Materials for Series Resistance Reduction
216th ECS Meeting, Vienna, Austria, October 4 – 9, 2009
Yee-Chia Yeo, Rinus T.P. Lee

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33: Single Silicide Comprising Nickel-Dysprosium Alloy for Integration in p-and n-FinFETs with Independent Control of Contact Resistance by Aluminum Implant
Symposium on VLSI Technology, Honolulu, HI, USA, June 16-18, 2009
Mantavya Sinha, Rinus T.P. Lee, Sivasubramaniam Nandini Devi, Guo-Qiang Lo, Eng Fong Chor, Yee-Chia Yeo

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32: Sulfur Segregation at the Platinum Silicide: Silicon:Carbon Interface for Electron Barrier Height Reduction: An Approach to Enable Independent Control of Contact Resistances for n- and p-channel FinFETs with a Single Metal Silicide
European MRS Spring Meeting, Strasbourg, France, June 8 – 12, 2009
R.T.P. Lee, D.Z. Chi, and Y.C. Yeo

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31: Integration of Al segregated NiSiGe/SiGe Source/Drain Contact Technology in p-FinFETs for Drive Current Enhancement
215th ECS Meeting, San Francisco, CA, May 24 – 29, 2009
Mantavya Sinha, Rinus T.P. Lee, Sivasubramaniam Nandini Devi, Guo-Qiang Lo, Eng Fong Chor, Yee-Chia Yeo

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30: p-FinFETs with Al Segregated NiSi/p+-Si Source/Drain Contact Junction for Series Resistance Reduction
VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 27 – 29, 2009
Mantavya Sinha, Rinus T.P. Lee, Sivasubramaniam Nandini Devi, Guo-Qiang Lo, Eng Fong Chor, Yee-Chia Yeo

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29: Schottky-Barrier Height Tuning of Nickel Silicide on Epitaxial Silicon-Carbon Films with High Substitutional Carbon Content
International Conference on Solid State Devices and Materials (SSDM), Ibaraki, Japan, September 23-26, 2008
P. S. Y. Lim, R. T. P. Lee, A. E. J. Lim, A. T. Y. Koh, M. Sinha, D. Z. Chi, Y. C. Yeo

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28: 5nm Gate Length NW-FETs and Planar UTB-FETs with Pure Ge S/D Stressors and Laser-Free Melt-Enhanced Dopant Diffusion and Activation Technique
Symposium on VLSI Technology, Honolulu, HI, USA, June 17 – 19, 2008
Tsung-Yang Liow, Kian-Ming Tan, Rinus T.P. Lee, Ming Zhu, Ben L-H Tan, Ganesh S. Samudra, N Balasubramanian, Yee-Chia Yeo

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27: Novel and Cost-Efficient Single Metallic Silicide Integration Solution with Dual Schottky-Barrier Achieved by Aluminum Inter-Diffusion for FinFET CMOS Technology with Enhanced Performance
Symposium on VLSI Technology, Honolulu, HI, USA, June 17 – 19, 2008
Rinus T.P. Lee, Alvin T.Y. Koh, W. W. Fang, K.M. Tan, Andy E.J. Lim, T.Y. Liow, S.Y. Chow, A. M Yong, H.S. Wong, G.Q. Lo, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo

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26: Selenium Co-implantation and Segregation as a New Contact Technology for Nanoscale SOI N-FETs featuring NiSi:C formed on Si:C S/D S Stressors
Symposium on VLSI Technology, Honolulu, HI, USA, June 17 – 19, 2008
H.S. Wong, F.Y. Liu, K.W. Ang, S.M. Koh, Alvin T.Y. Koh, T.Y. Liow, Rinus T. P. Lee, Andy E.J. Lim, W.W. Fang, M. Zhu, L. Chan, N Balasubramaniam, G. Samudra, Yee-Chia Yeo

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25: Strained FinFETs with In-situ Doped Si 1-y C y S/D Stressors: Performance Boost with Lateral Stressor Encroachment and High Substitutional Carbon Content
VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr 21 – 23, 2008
T.Y. Liow, K.M. Tan, Doran Weeks, Rinus T.P. Lee, Ming Zhu, K.M. Hoe, C.H. Tung, M Bauer, J. Spear, S. G Thomas, Ganesh S. Samudra, N Balasubramanian, Yee-Chia Yeo

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24: A New Salicidation Process with Solid Antimony Segregation for Achieving Sub-0.1 eV Effective Schottky Barrier Height  and Parasitic Series Resistance Reduction in N-Channel Transistors
VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 21 – 23, 2008
Hoong-Shing Wong, Alvin Tian-Yi Koh, Hock-Chun Chin, Rinus Tek-Po Lee, Lap Chan, Ganesh Samudra, Yee-Chia Yeo

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23: Photoemission Study of Energy Band Alignment of Ge2Sb2Te5 and Common CMOS Materials
MRS Spring Meeting, San Francisco, CA, USA, March 24 – 28, 2008
Lina Wei-Wei Fang, Ji-Sheng Pan, Andy Eu-Jin Lim, Rinus Tek-Po Lee, Minghua Li, Rong Zhao, Luping Shi, Tow-Chong Chong, Yee-Chia Yeo

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22: Formation of Nickel-Based Germanosilicide Contacts on Silicon-Germanium-Tin (Si1-x-yGexSny) Source/Drain Stressors
MRS Spring Meeting, San Francisco, CA, USA, March 24 – 28, 2008
R.T.P. Lee, F.Y. Liu, K.M. Tan, A.E.-J. Lim, T.Y. Liow, S. Tripathy, G.S. Samudra, D.Z. Chi, and Y.C. Yeo

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21: Contact Technology for Germanium-Tin (GeSn) Source/Drain using Nickel and Nickel-Platinum Alloys
MRS Spring Meeting, San Francisco, CA, USA, March 24 – 28, 2008
G.H. Wang, E.-H. Toh, R.T.P. Lee, X.-C. Wang, D.H.L. Seng, S. Tripathy, Y.- L. Foo, G. Samudra, and Y.-C. Yeo

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20: Sub-30 nm FinFETs with Schottky-Barrier Source/Drain Featuring Complementary Metal Silicides and Fully-Silicided Gate for P-FinFETs
MRS Spring Meeting, San Francisco, CA, USA, April 9 – 13, 2007
Rinus Tek Po Lee, Kian-Ming Tan, Tsung-Yang Liow, Andy Eu-Jin Lim, Guo-Qiang Lo, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo

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19: Interface Dipole Mechanism and NMOS Ni-FUSI Gate Work Function Engineering using Rare-Earth Metal (RE)-Based Dielectric Interlayers
International Semiconductor Device Research Symposium (ISDRS), Maryland, MD, Dec  12 – 14, 2007
Andy Eu-Jin Lim, Wei-Wei Fang, Fangyue Liu, Rinus T.P. Lee, Ganesh S Samudra, Dim-Lee Kwong, Yee-Chia Yeo

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18: A New Liner Stressor with Very High Intrinsic Stress (≫ 6 GPa) and Low Permittivity Comprising Diamond-Like Carbon for Strained P-Channel Transistors
International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 10 – 12, 2007
K.M. Tan, Ming Zhu, Wei-Wei Fang, Mingchu Yang, Tsung-Yang Liow, Rinus T.P. Lee, Keat Mun Hoe, Chih-Hang Tung, N Balasubramanian, Ganesh S Samudra, Yee-Chia Yeo

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17: Route to Low Parasitic Resistance in MuGFETs with Silicon-Carbon S/D: Integration of Novel Low Barrier Ni(M)Si:C Metal Silicides and Pulsed Laser Annealing
International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 10 – 12, 2007
Rinus Tek-Po Lee, Alvin Tian-Yi Koh, Fang-Yue Liu, Wei-Wei Fang, Tsung-Yang Liow, Kian-Ming Tan, Poh-Chong Lim, Andy Eu-Jin Lim, Ming Zhu, Keat-Mun Hoe, Chih-Hang Tung, Guo-Qiang Lo, Xincai Wang, David Kuang-Yong Low, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo

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16: Strained N-channel FinFETs with High-Stress Nickel Silicide-Carbon Contacts and Integration with FUSI Metal Gate Technology
International Conference on Solid State Devices and Materials (SSDM), Ibaraki, Japan, September 18 – 21, 2007
Tsung-Yang Liow, R.T.P Lee, K.M. Tan, M. Zhu, K.M. Hoe, G.S. Samudra, N Balasubramanian, Y.C. Yeo

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15: Contact Technology Employing Nickel-Platinum Germanosilicide Alloys for p-Channel FinFETs with Silicon-Germanium Source and Drain Stressors
International Conference on Solid State Devices and Materials (SSDM), Ibaraki, Japan, September 18 – 21, 2007
R.T.P. Lee, K.M. Tan, A. E.-J. Lim, T.Y. Liow, X.C. Chen, M. Zhu, A.T.Y. Koh, K.M. Hoe, S.Y. Chow, G.Q. Lo, G.S. Samudra, D.Z. Chi, Y.C. Yeo

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14: Strain Enhancement in Spacer-Less N-channel FinFETs with Silicon-Carbon Source and Drain Stressors
37th European Solid State Device Research Conference (ESSDERC), Munich, Germany, September 11 – 13, 2007
Tsung-Yang Liow, Kian-Ming Tan, Rinus T.P. Lee, Ming Zhu, Keat-Mun Hoe, Ganesh S Samudra, N Balasubramanian, Yee-Chia Yeo

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13: Band edge NMOS Work Function for Nickel Fully-Silicided (FUSI) Gate obtained by the Insertion of Novel Y-, Tb-, and Yb-based Interlayers
37th European Solid State Device Research Conference (ESSDERC), Munich, Germany, September 11 – 13, 2007
Andy Eu-Jin Lim, Rinus TP Lee, Xin Peng Wang, Wan Sik Hwang, Chih-Hang Tung, Doreen MY Lai, Ganesh Samudra, Dim-Lee Kwong, Yee-Chia Yeo

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12: Novel Epitaxial Nickel Aluminide-Silicide with Low Schottky-Barrier and Series Resistance for Enhanced Performance of Dopant-Segregated S/D N-MuGFETs
Symposium on VLSI Technology, Kyoto, Japan, June 12 – 16, 2007
Rinus TP Lee, T.Y. Liow, K.M. Tan, Andy E.J. Lim, Chee-Seng Ho, Keat-Mum Hoe, M.Y. Lai, Thomas Osipowicz, Guo-Qiang Lo, Ganesh Samudra, Dong-Zhi Chi, Yee-Chia Yeo

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11: Material and Electrical Characterization of Nickel Silicide-Carbon as Contact Metal to Silicon-Carbon Source and Drain Stressors
MRS Spring Meeting, San Francisco, CA, USA, April 9 – 13, 2007
Rinus Tek Po Lee, Li-Tao Yang, Kah-Wee Ang, Tsung-Yang Liow, Kian-Ming Tan, Andrew See-Weng Wong, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo

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10: Carrier Transport Characteristics of sub-30 nm Strained n-Channel FinFETs Featuring Si:C S/D Regions and Methods for Further Performance Enhancement
International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 11 – 13, 2006
Tsung-Yang Liow, Kian-Ming Tan, Hock-Chun Chin, Rinus T.P. Lee, Chih-Hang Tung, Ganesh S Samudra, N Balasubramanian, Yee-Chia Yeo

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09: Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in n-Channel Multiple-Gate Transistors with Sub-35nm Gate Length
International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 11 – 13, 2006
Rinus T.P. Lee, T.Y. Liow, K.M. Tan, Andy E.J. Lim, H.S. Wong, P.C. Lim, Doreen MY Lai, Guo-Qiang Lo, Chih-Hang Tung, Ganesh Samudra, Dong-Zhi Chi, Yee-Chia Yeo

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08: Sub-30 nm Strained p-Channel FinFETs with Condensed SiGe Source/Drain Stressors
International Conference on Solid State Devices and Materials (SSDM), Yokohama, Japan, September 12 – 15, 2006
K.M. Tan, T.Y. Liow, R.T.P. Lee, K.J. Chui, C.H. Tung, N. Balasubramanian, G.S. Samudra, W.J. Yoo, Y.C. Yeo

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07: Sub-30 nm P-channel Schottky Source/Drain FinFETs: Integration of Pt3Si FUSI Metal Gate and High-K Dielectric
International Conference on Solid State Devices and Materials (SSDM), Yokohama, Japan, September 12 – 15, 2006
R.T.P. Lee, K.M. Tan, A.E-J Lim, T.Y. Liow, G.Q. Lo, G. Samudra, D.Z. Chi, Y.C. Yeo

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06: Strained n-Channel FinFETs with 25 nm Gate Length and Silicon-Carbon Source/Drain Regions for Performance Enhancement
Symposium on VLSI Technology, Honolulu, HI, USA, June 13 – 17, 2006
T-Y Liow, K-M Tan, R. Lee, Anyan Du, C-H Tung, G Samudra, W-J Yoo, N Balasubramanian, Y-C Yeo

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05: Material and Electrical Characterization of Ni-and Pt-Germanides for p-Channel Germanium Schottky Source/Drain Transistors
International Workshop on Junction Technology (IWJT), Shanghai, China, May 15 – 16, 2006
H.B. Yao, C.C. Tan, S.L. Liew, C.T. Chua, C.K. Chua, R. Li, R.T.P. Lee, S.J. Lee, D.Z. Chi

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04: Process-Induced Strained p-MOSFET Featuring Nickel-Platinum Silicided Source/Drain
MRS Spring Meeting, San Francisco, CA, USA, April 17 – 21, 2006
Rinus Tek Po Lee, Tsung-Yang Liow, Kian-Ming Tan, Kah-Wee Ang, King-Jien Chui, Qiang-Lo Guo, Ganesh Samudra, Dong-Zhi Chi, Yee-Chia YeO

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03: Material and Electrical Characterization of Nickel Germanide for p-Channel Germanium Schottky Source/Drain Transistors
International Conference on Solid State Devices and Materials (SSDM), Kobe, Japan, September 12 – 15, 2005
R.T.P. Lee, S.L. Liew, B Balakrishnan, K.Y. Lee, Y.C. Yeo, D.Z. Chi

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02: (Invited) Addressing Materials and Process-Integration Issues of NiSi Silicide Process using Impurity Engineering
International Workshop on Junction Technology (IWJT), Shanghai, China, March 16, 2004
D.Z. Chi, R.T.P. Lee, S.J. Chua

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01: NiSi formation in the Ni (Ti)/SiO2/Si System
MRS Spring Meeting, San Francisco, CA, USA, March 12 – 16, 2004
R.T.P. Lee, D.Z. Chi, S.J. Chua