30: Low Resistance Liner

US12666933 B2, Jun 23, 2026, Tek Po Rinus Lee, Gyanaranjan Pattanaik, Kenichi Imakita

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29: Single Diffusion Breaks Including Stacked Dielectric Layers

US11545574 B2, Jan 3, 2023, Haiting Wang, Rinus Lee, Sipeng Gu, Yue Hu

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28: Asymmetric source/drain structures in a semiconductor device

US11362178 B2, June 14, 2022, Jeff Shu, Baofu Zhu, Rinus Tek Po Lee​​

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27: Semiconductor Devices with Low Resistance Gate Structures

US11145716 B1, Oct 12, 2021, Lee Rinus Tek Po, Jiehui Shu

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26: Multiple Threshold Voltage Devices

US11094598 B2, Aug 17, 2021, Bharat V Krishnan, Lee Rinus Tek Po, Jiehui Shu, Hyung Yoon Choi

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25: Mask-Free Methods of Forming Structures in a Semiconductor Device

US11004953 B2, May 11, 2021, Lee Rinus Tek Po, Zang Hui, Jiehui Shu, Yu Hong, Hong Wei

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24: Mask-Free Methods of Forming Structures in a Semiconductor Device

US10896853 B2, Jan 19, 2021, Jiehui Shu, Lee Rinus Tek Po, Hong Wei, Zang Hui, Yu Hong

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23: Devices with Highly Active Acceptor Doping and Method of Production Thereof

US10886178 B2, Jan 5, 2021, Lee Rinus Tek Po, Annie Levesque, Qun Gao, Hui Zang, Rishikesh Krishnan, Bharat Krishnan, Curtis Durfee

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22: Spacer Structures for a Transistor Device

US10872979 B2, Dec 22, 2020, Hui Zang, Chung Foong Tang, Guowei Xu, Haiting Wang, Yue Zhong, Ruilong Xie, Lee Rinus Tek Po, Scott Beasor

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​21: Methods of Forming Spacers Adjacent to Gate Structures of a Transistor Device

US10629739 B2, Apr 21, 2020, Zang Hui, Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong, Ruilong Xie, Lee Rinus Tek Po, Scott Beasor

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20: Memory Array with Buried Bitlines below Vertical Field Effect Transistors of Memory Cells and a Method of Forming the Memory Array

US10418365 B2, Sept 17, 2019, Zang Hui, Ciavatti Jerome, Lee Rinus Tek Po

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19: Common Metal Contact Regions having Different Schottky Barrier Heights and Methods of Manufacturing Same

US10276683 B2, Apr 30, 2019, Rinus Tek Po Lee, Jinping Liu, Ruilong Xie

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18: Methods, Apparatus, and Manufacturing System for Self-Aligned Patterning of Contacts in a Vertical Field Effect Transistor

US10263122 B1, Apr 16, 2019, Zang Hui, Xie Ruilong, Rinus Tek Po Lee, Lars Liebmann

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17: Method for Forming a Protection Device having An Inner Contact Spacer and Resulting Devices

US10242982 B2, Mar 26, 2019, Xie Ruilong, Katsunori Onishi, Rinus Tek Po Lee

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16: Vertical-Transport Transistors with Self-Aligned Contacts

US10230000 B2, Mar 12, 2019, Emilie Bourjot, Daniel Chanemougame, Rinus Tek Po Lee, Xie Ruilong, Hui Zang

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15: Microwave Annealing of Flowable Oxides with Trap Layer

US10211045 B1, Feb 19, 2019, Rishikesh Krishnan, Joseph K. Kassim, Bharat V. Krishnan, Joseph F. Shepard, Rinus Tek Po Lee, Yiheng Xu

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14: Methods, Apparatus and System for Vertical FinFET Device with Reduced Parasitic Capacitance

US10204904 B2, Feb 12, 2019, Zang Hui, Rinus Tek Po Lee

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13: Integrated Circuit Products that Include FinFET Devices and a Protection Layer Formed on An Isolation Region

US10170544 B2, Jan 1, 2019, Xie Ruilong, Christopher Prindle, Ming Gyu Sung, Rinus Tek Po Lee

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12: FinFETs with Strained Channels and Reduced on State Resistance

US10134876 B2, Nov 20, 2018 |PDF| Bharat Krishnan, Timothy McArdle, Rinus Tek Po Lee, Shishir Ray, Akshey Sehgal

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11: Memory Array with Buried Bitlines Below Vertical Field Effect Transistors of Memory Cells and a Method of Forming the Memory Array

US10134739 B1, Nov 20, 2018, Zang Hui, Jerome Ciavatti, Rinus Tek Po Lee

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10: Semiconductor Structure including Two-Dimensional and Three-Dimensional Bonding Materials

US10121706 B2, Nov 6, 2018, Rinus T.P. Lee, Bharat Krishnan, Zang Hui, Matthew Stoker

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09: Buried Contact Structures for a Vertical Field-Effect Transistor

US10109714 B2 Oct 23, 2018, Zang Hui, Rinus Tek Po Lee

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08: Nanosheet FET with Full Dielectric Isolation

US10103238 B1, Oct 16, 2018, Zang Hui, Rinus Tek Po Lee, Haigou Huang, Chanro Park, Ming Gyu Sung, Xie Ruilong

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07: Methods of Forming a Protection Layer on An Isolation Region of IC products comprising FinFET Devices

US9876077 B1, Jan 23, 2018, Xie Ruilong, Christopher Prindle, Ming Gyu Sung, Rinus Tek Po Lee

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06: Buried Contact Structures for a Vertical Field-Effect Transistor

US9831317 B1, Nov. 28, 2017, Hui Zang, Tek Po Rinus Lee

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05: Common Metal Contact Regions having Different Schottky Barrier Heights and Methods of Manufacturing Same

US9812543 B2, Nov 07, 2017, Rinus Tek Po Lee, Jinping Liu, Ruilong Xie

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04: Forming Symmetrical Stress Liners for Strained CMOS Vertical Nanowire Field-Effect Transistors

US9570552 B1, Feb, 14, 2017, Rinus Tek Po Lee, Jinping Liu

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03: Metal Alloy with An Abrupt Interface to III-V Semiconductor

US8829567 B2, Sept 9, 2014, Rinus Tek Po Lee, Tae Woo Kim, Man Hoi Wong, Richard Hill

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02: Silicide Formed from Ternary Metal Alloy Films

US7335606 B2, Feb 26, 2008, Dongzhi Chi, Tek Po Rinus, Soo Jin Chua

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01: Forming an Electrical Contact on An Electronic Component

US7015132 B2, Mar 06, 2006, Syamal Kumar Lahiri, Rinus Tek Po Lee, Zuruzi Bin Abu Samah